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issue 06

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This commit is contained in:
agra
2026-03-03 16:18:58 +02:00
parent 23f444033a
commit 0336f361c7
7 changed files with 181 additions and 33 deletions
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6
src/core.zig
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@@ -97,7 +97,7 @@ pub const Compilation = struct {
pub fn generateCode(self: *Compilation) !void {
// Heap-allocate the IR module so its address is stable during emit
const ir_mod_ptr = try self.allocator.create(ir.Module);
ir_mod_ptr.* = self.lowerToIR();
ir_mod_ptr.* = try self.lowerToIR();
var emitter = ir.LLVMEmitter.init(self.allocator, ir_mod_ptr, "sx_module", self.target_config);
emitter.emit();
// IR module is no longer needed after LLVM IR has been generated
@@ -131,7 +131,7 @@ pub const Compilation = struct {
}
/// Lower the parsed AST to the sx IR module (shadow pipeline).
pub fn lowerToIR(self: *Compilation) ir.Module {
pub fn lowerToIR(self: *Compilation) !ir.Module {
const root = self.resolved_root orelse self.root orelse return ir.Module.init(self.allocator);
var module = ir.Module.init(self.allocator);
//TODO: find a better place for this
@@ -142,7 +142,9 @@ pub const Compilation = struct {
lowering.main_file = self.file_path;
lowering.resolved_root = root;
lowering.target_config = self.target_config;
lowering.diagnostics = &self.diagnostics;
lowering.lowerRoot(root);
if (self.diagnostics.hasErrors()) return error.CompileError;
return module;
}