feat(asm): read-write + place outputs

Implements read-write (`+r` / `+{reg}`) `-> @place` outputs. LLVM has
no `+` constraint, so a read-write place lowers to:

  - an output `=` constraint (return slot, stored back through the
    place after the call), with the leading `+` rewritten to `=`; plus
  - a TIED input constraint (the decimal index of that output) appended
    after the regular inputs, seeded with the place's loaded value
    passed as a call arg.

Tied inputs are appended last so existing operand indices (%[name] ->
${N}) are undisturbed; asmOperandIndex stays correct. Lowering no longer
rejects `+` (indirect `*` still rejected). emitInlineAsm grows the
arg/param arrays by the rw count, loads each seed, and emits the tied
constraint.

Verified by running: increment-in-place (41 -> 42) and a mixed case
(rw place + regular input + value output) producing the textbook
"=r,=r,r,0" constraint with correct ${N} indices. 1650 flipped from
the rejection lock to a runnable aarch64-pinned example (ir-only
elsewhere). zig build test green (658 corpus, 446 unit).

examples/expected/1650-platform-asm-rw-place.build

@@ -0,0 +1 @@
+{ "target": "macos" }

examples/expected/1650-platform-asm-rw-place.exit

@@ -1 +1 @@
-1
+42

examples/expected/1650-platform-asm-rw-place.ir

@@ -0,0 +1,20 @@
+
+; Function Attrs: nounwind
+define internal i64 @compute() #0 {
+entry:
+  %alloca = alloca i64, align 8
+  store i64 41, ptr %alloca, align 8
+  %asm.rw.seed = load i64, ptr %alloca, align 8
+  %asm = call i64 asm sideeffect "add ${0}, ${0}, #1", "=r,0"(i64 %asm.rw.seed)
+  store i64 %asm, ptr %alloca, align 8
+  %load = load i64, ptr %alloca, align 8
+  ret i64 %load
+}
+
+; Function Attrs: nounwind
+define i32 @main() #0 {
+entry:
+  %call = call i64 @compute()
+  %ca.tr = trunc i64 %call to i32
+  ret i32 %ca.tr
+}

examples/expected/1650-platform-asm-rw-place.stderr

@@ -1,5 +1 @@
-error: read-write (`+`) asm outputs are not yet implemented; use a write-only `=` output
-  --> examples/1650-platform-asm-rw-place.sx:8:5
-   |
- 8 |     asm volatile { "add %[v], %[v], #1", [v] "+r" -> @x };
-   |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+