feat(asm): Phase C.0 — add inline_asm IR op (lock, no behavior change)

Adds the `inline_asm: InlineAsm` opcode to the IR Op union (inst.zig): interned
template + operand list (role/name/constraint/operand) + interned clobber names
+ has_side_effects; the result rides on Inst.ty (void / scalar / tuple).

The new variant forces coverage in the exhaustive Op switches:
- interp.zig: loud bailDetail — inline asm is never comptime-evaluable.
- print.zig: an IR-dump arm.
- emit_llvm.zig: a @panic TRIPWIRE — emit lands in Phase D, and until then
  lowerAsmExpr still bails, so no inline_asm op is ever created. Reaching emit
  would mean lowering switched over before emit was ready; crash loudly rather
  than miscompile.

No behavior change: lowering still bails, the op is constructed only in the new
`inline_asm op shape` unit test (inst.test.zig).

zig build test green (652 corpus, 446 unit).

src/ir/interp.zig

@@ -1015,6 +1015,8 @@ pub const Interpreter = struct {
             .objc_msg_send => return bailDetail("#objc_call not available at comptime (no Obj-C runtime)"),
             // Same story for JNI — no JVM at compile time.
             .jni_msg_send => return bailDetail("#jni_call not available at comptime (no JVM)"),
+            // Inline asm executes target machine code — never comptime-evaluable.
+            .inline_asm => return bailDetail("inline assembly requires native execution; not available at comptime"),
 
             // ── Block params ────────────────────────────────────
             .block_param => {