atomics A.1a: RMW ops + recognizer + methods, emit bails (lock)

fetch_add/sub/and/or/xor/min/max wired end-to-end except LLVM emission (bails
loudly; A.1b makes it real). New IR op atomic_rmw + RmwKind (no nand) +
AtomicRmw{ptr, operand, val_ty, ordering, kind}. print arm; comptime_vm arm
implements real single-thread RMW (load/compute/store/return-old, signed|unsigned
min/max from val_ty). Recognizer extended (rmwKindFromName) — RMW restricted to
integer T (float fadd / pointer RMW out of scope, rejected loudly); all orderings
valid for RMW. Methods fetch_* on Atomic($T) with comptime $o: Ordering.
examples/1701 locked to the bail. Suite green (716/0).

src/ir/emit_llvm.zig

@@ -1567,6 +1567,7 @@ pub const LLVMEmitter = struct {
             .store => |st| self.ops().emitStore(st),
             .atomic_load => |a| self.ops().emitAtomicLoad(instruction, a),
             .atomic_store => |a| self.ops().emitAtomicStore(a),
+            .atomic_rmw => |a| self.ops().emitAtomicRmw(instruction, a),
             // ── Globals ───────────────────────────────────────────
             .global_get => |gid| self.ops().emitGlobalGet(instruction, gid),
             .global_addr => |gid| self.ops().emitGlobalAddr(gid),