atomics A.1a: RMW ops + recognizer + methods, emit bails (lock)

fetch_add/sub/and/or/xor/min/max wired end-to-end except LLVM emission (bails
loudly; A.1b makes it real). New IR op atomic_rmw + RmwKind (no nand) +
AtomicRmw{ptr, operand, val_ty, ordering, kind}. print arm; comptime_vm arm
implements real single-thread RMW (load/compute/store/return-old, signed|unsigned
min/max from val_ty). Recognizer extended (rmwKindFromName) — RMW restricted to
integer T (float fadd / pointer RMW out of scope, rejected loudly); all orderings
valid for RMW. Methods fetch_* on Atomic($T) with comptime $o: Ordering.
examples/1701 locked to the bail. Suite green (716/0).

src/ir/inst.zig

@@ -164,6 +164,7 @@ pub const Op = union(enum) {
     // ── Atomics ─────────────────────────────────────────────────────
     atomic_load: AtomicLoad, // atomic load from pointer with memory ordering
     atomic_store: AtomicStore, // atomic store to pointer with memory ordering
+    atomic_rmw: AtomicRmw, // atomic read-modify-write; result is the OLD value
 
     // ── Struct ops ──────────────────────────────────────────────────
     struct_init: Aggregate, // construct struct from field values
@@ -319,6 +320,20 @@ pub const AtomicStore = struct {
     ordering: AtomicOrdering,
 };
 
+/// Atomic read-modify-write operation kind. `min`/`max` pick the signed vs
+/// unsigned LLVM op (`Min`/`Max` vs `UMin`/`UMax`) from the value type's
+/// signedness at emit time. No `nand` (deliberately omitted).
+pub const RmwKind = enum { add, sub, @"and", @"or", xor, min, max };
+
+pub const AtomicRmw = struct {
+    ptr: Ref,
+    operand: Ref,
+    /// Declared type of the operand / result (drives byte width + signedness).
+    val_ty: TypeId = .void,
+    ordering: AtomicOrdering,
+    kind: RmwKind,
+};
+
 pub const Conversion = struct {
     operand: Ref,
     from: TypeId,