atomics A.0c: harden guards (scalar-kind, ordering validity, align bail)
Adversarial review of A.0 found two silent-wrong defects reachable via the public atomic_load/atomic_store intrinsics (raw LLVM verifier errors, not clean sx diagnostics) + a latent alignment fallback. All fixed: - scalar-kind allowlist (call.zig): the size-only T guard admitted same-sized aggregates ([8]u8, 8-byte structs) -> invalid 'load atomic [8 x i8]'. Now an allowlist switch (integer/float/bool/pointer/enum/vector) rejects loudly. - per-op ordering validity (call.zig): load cannot release/acq_rel, store cannot acquire/acq_rel -> loud diagnostic instead of invalid LLVM. - val_ty align fallback (ops.zig): the 'else .i64' (align 8) default would over-align a sub-8 store -> now bails loudly on a missing val_ty. Locked by examples 1130 (non-scalar) + 1131 (bad ordering). Suite green (713/0).
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@@ -4,7 +4,27 @@ Companion to [PLAN-ATOMICS.md](PLAN-ATOMICS.md). Update after every step (one st
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time, per the cadence rule). New corpus category: `17xx`.
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## Last completed step
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**A.0b (green) — DONE.** Real atomic load/store emission: `LLVMBuildLoad2`/`LLVMBuildStore`
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**A.0c (guard hardening) — DONE.** Adversarial review of A.0 found two CRITICAL silent-wrong
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defects (raw LLVM verifier errors leaking via the public intrinsics) + a latent align
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fallback; all fixed:
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- **Scalar-kind guard** (call.zig): the size-only check admitted same-sized aggregates
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(`[8]u8`, 8-byte struct) → invalid `load atomic [8 x i8]`. Now an allowlist switch
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(integer/float/bool/pointer/enum/vector) rejects non-scalars loudly.
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- **Per-op ordering validity** (call.zig): a load can't `release`/`acq_rel`, a store can't
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`acquire`/`acq_rel` (LLVM rejects). Now a loud diagnostic, not invalid IR.
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- **`val_ty` align fallback** (ops.zig): the `else .i64` (align-8) default would over-align a
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sub-8 store → now bails loudly if `val_ty` is missing (a compiler bug, not a guess).
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- Locked by `examples/1130-diagnostics-atomic-nonscalar.sx` +
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`1131-diagnostics-atomic-bad-ordering.sx`. Suite green (713, 0 failed).
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**Capability landed (worker, commit 3c4305f):** comptime enum value params — `$o: Ordering`
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now binds the variant tag and resolves in the body; during LOWERING the tag is readable via
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`self.comptimeIntNamed("<param>")` → `?i64`. This unblocks A.0.5 (full ordering surface).
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Worker limitation: `.tagged_union` constraints were skipped — user wants this lifted (any
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value should be comptime-able); separate generalization worker spawned.
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### Earlier — A.0b (green)
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Real atomic load/store emission: `LLVMBuildLoad2`/`LLVMBuildStore`
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+ `LLVMSetOrdering` + mandatory `LLVMSetAlignment`, ordering via an explicit
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sx-tag→`LLVMAtomicOrdering` switch (`llvmOrdering`). `examples/1700` green (7/42/43); IR
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shows `load atomic i64, ptr … seq_cst, align 8` + `store atomic …`. Added unit test
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@@ -75,3 +95,6 @@ Full atomic load/store plumbing with LLVM emission deliberately bailing loudly;
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- **A.0b** — real atomic load/store emission (LLVMBuildLoad2/Store + SetOrdering +
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SetAlignment; explicit sx→LLVM ordering switch). 1700 green (7/42/43, `load atomic …
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seq_cst, align 8`). Unit test added. Suite green (710 + units).
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- **A.0c** — guard hardening from the adversarial review: scalar-kind allowlist + per-op
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ordering validity (call.zig), val_ty align bail (ops.zig), + diagnostic examples
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1130/1131. Suite green (713/0). (comptime enum value params landed via worker 3c4305f.)
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