ERR/E3.0 (slice 1): thread source spans into IR instructions

Foundation for DWARF line-info (E3.0). The `Inst.span` field existed but was
never populated — `emit()` always passed the empty `{0,0}` default, so every
instruction had no source location (the lone reader, the interp's comptime
bail-offset, was always 0).

- Builder gains a `current_span`; `emit`/`emitVoid` stamp it onto each
  instruction.
- `lowerExpr` / `lowerStmt` set `current_span` from the AST node's span on
  entry and restore it on exit (save/restore), so a parent's later emits keep
  the parent's span after a child lowers; the empty default is skipped so
  synthetic nodes don't reset a meaningful enclosing span.

Behavior-neutral: codegen never reads spans, and the only consumer (the interp
bail-offset) merely gains real offsets. 290 examples pass unchanged, no `.ir`
snapshot drift. New unit test asserts an emitted `add` carries its `a + b` span.

Next (slice 2): bind `llvm-c/DebugInfo.h`, emit DICompileUnit / DISubprogram /
DIFile / DILocation from these spans, gate on debug/trace mode.

src/ir/lower.test.zig

@@ -86,6 +86,66 @@ test "lower: simple function with arithmetic" {
     try std.testing.expect(std.mem.indexOf(u8, output, "add %") != null or std.mem.indexOf(u8, output, "ret %") != null);
 }
 
+test "lower: instructions carry their AST node's source span (ERR E3.0)" {
+    const alloc = std.testing.allocator;
+    var module = ir_mod.Module.init(alloc);
+    defer module.deinit();
+
+    // probe :: (a: s64, b: s64) -> s64 { return a + b; } — the `a + b` node
+    // gets a distinctive span so we can find the emitted `add` instruction and
+    // assert it was stamped (not left at the empty {0,0} default).
+    const a_type = alloc.create(Node) catch unreachable;
+    a_type.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .type_expr = .{ .name = "s64", .is_generic = false } } };
+    const b_type = alloc.create(Node) catch unreachable;
+    b_type.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .type_expr = .{ .name = "s64", .is_generic = false } } };
+    const ret_type = alloc.create(Node) catch unreachable;
+    ret_type.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .type_expr = .{ .name = "s64", .is_generic = false } } };
+    const a_ident = alloc.create(Node) catch unreachable;
+    a_ident.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .identifier = .{ .name = "a" } } };
+    const b_ident = alloc.create(Node) catch unreachable;
+    b_ident.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .identifier = .{ .name = "b" } } };
+    const add_expr = alloc.create(Node) catch unreachable;
+    add_expr.* = .{ .span = .{ .start = 42, .end = 47 }, .data = .{ .binary_op = .{ .op = .add, .lhs = a_ident, .rhs = b_ident } } };
+    const ret_stmt = alloc.create(Node) catch unreachable;
+    ret_stmt.* = .{ .span = .{ .start = 30, .end = 50 }, .data = .{ .return_stmt = .{ .value = add_expr } } };
+    const body = alloc.create(Node) catch unreachable;
+    const stmts: []const *Node = &.{ret_stmt};
+    body.* = .{ .span = .{ .start = 0, .end = 0 }, .data = .{ .block = .{ .stmts = stmts } } };
+    defer {
+        alloc.destroy(a_type);
+        alloc.destroy(b_type);
+        alloc.destroy(ret_type);
+        alloc.destroy(a_ident);
+        alloc.destroy(b_ident);
+        alloc.destroy(add_expr);
+        alloc.destroy(ret_stmt);
+        alloc.destroy(body);
+    }
+
+    const params: []const ast.Param = &.{
+        .{ .name = "a", .name_span = .{ .start = 0, .end = 0 }, .type_expr = a_type },
+        .{ .name = "b", .name_span = .{ .start = 0, .end = 0 }, .type_expr = b_type },
+    };
+    const fn_decl = ast.FnDecl{ .name = "probe", .params = params, .return_type = ret_type, .body = body };
+
+    var lowering = Lowering.init(&module);
+    lowering.lowerFunction(&fn_decl, "probe", false);
+
+    // Find the `add` instruction and assert it carries the `a + b` span.
+    const func = module.getFunction(FuncId.fromIndex(0));
+    var found = false;
+    for (func.blocks.items) |blk| {
+        for (blk.insts.items) |inst| {
+            if (inst.op == .add) {
+                try std.testing.expectEqual(@as(u32, 42), inst.span.start);
+                try std.testing.expectEqual(@as(u32, 47), inst.span.end);
+                found = true;
+            }
+        }
+    }
+    try std.testing.expect(found);
+}
+
 test "lower: if/else generates basic blocks" {
     const alloc = std.testing.allocator;
     var module = ir_mod.Module.init(alloc);