atomics A.3b: real swap (xchg) + fence emission + unit test (green)

emitAtomicRmw xchg arm (swap) and emitAtomicFence (LLVMBuildFence) now real.
examples/1703 (swap old=7/now=42, 'atomicrmw xchg') + 1704 (fence release/acquire/
seq_cst) green. Unit test 'emit: atomic swap (xchg) + fence'. Stream A
(atomics) is feature-complete: load/store, RMW (add/sub/and/or/xor/min/max),
compare_exchange[_weak], swap, fence. Suite green (721/0).

src/ir/emit_llvm.test.zig

@@ -280,6 +280,35 @@ test "emit: atomic rmw (add + signed/unsigned min)" {
     try std.testing.expect(std.mem.indexOf(u8, ir_str, "atomicrmw umin") != null); // unsigned u64
 }
 
+test "emit: atomic swap (xchg) + fence" {
+    const alloc = std.testing.allocator;
+    var module = Module.init(alloc);
+    defer module.deinit();
+
+    var b = Builder.init(&module);
+
+    _ = b.beginFunction(str(&module, "f"), &.{}, .i64);
+    const entry = b.appendBlock(str(&module, "entry"), &.{});
+    b.switchToBlock(entry);
+
+    const p = b.alloca(.i64);
+    const five = b.constInt(5, .i64);
+    const old = b.emit(.{ .atomic_rmw = .{ .ptr = p, .operand = five, .val_ty = .i64, .ordering = .acq_rel, .kind = .xchg } }, .i64);
+    b.emitVoid(.{ .atomic_fence = .{ .ordering = .seq_cst } }, .void);
+    b.ret(old, .i64);
+    b.finalize();
+
+    var emitter = LLVMEmitter.init(alloc, &module, "test_swap_fence", .{});
+    defer emitter.deinit();
+    emitter.emit();
+
+    try std.testing.expect(emitter.verify());
+
+    const ir_str = emitter.dumpToString();
+    try std.testing.expect(std.mem.indexOf(u8, ir_str, "atomicrmw xchg") != null);
+    try std.testing.expect(std.mem.indexOf(u8, ir_str, "fence seq_cst") != null);
+}
+
 test "emit: atomic cmpxchg (strong + weak)" {
     const alloc = std.testing.allocator;
     var module = Module.init(alloc);