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atomics A.2a: CAS ops + recognizer + methods, emit bails (lock)

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compare_exchange/_weak wired end-to-end except LLVM emission (bails loudly;
A.2b makes it real). New IR op atomic_cmpxchg + AtomicCmpxchg{ptr, cmp, new,
val_ty, success_ordering, failure_ordering, weak}; result type = ?T (null =
SUCCESS, failure carries the actual value for retry). print arm; emit dispatch
-> emitAtomicCmpxchg (BAILS). comptime_vm arm does real single-thread CAS (read
actual / compare / store-on-equal / build ?T: success->none, failure->some;
weak == strong at comptime). Recognizer extended (atomic_cmpxchg/_weak, 6 args)
-- CAS restricted to INTEGER T (loud reject); BOTH orderings resolved via
atomicOrderingFromNode; dual-ordering validation (failure may not be
release/acq_rel nor stronger than success, via atomicOrderingRank). Methods
compare_exchange/_weak on Atomic($T) with comptime $success/$failure: Ordering.
examples/1702 locked to the bail; examples/1186 locks a rejected ordering pair.
Suite green (718/0).
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2026-06-20 10:44:31 +03:00
parent 68ed732b79
commit dca396ed1f
16 changed files with 226 additions and 12 deletions
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@@ -4,18 +4,30 @@ Companion to [PLAN-ATOMICS.md](PLAN-ATOMICS.md). Update after every step (one st
time, per the cadence rule). New corpus category: `17xx`.
## Last completed step
**A.1 (RMW) — DONE** (A.1a lock + A.1b green). `fetch_add/sub/and/or/xor` + `fetch_min/max`
→ LLVM `atomicrmw` (returns OLD value). New IR op `atomic_rmw` + `RmwKind` (no `nand`);
`LLVMBuildAtomicRMW` with binop from kind, signed/unsigned `Min/Max` from `val_ty`. RMW
restricted to INTEGER T (float fadd / pointer RMW out of scope, rejected loudly); all five
orderings valid for RMW. comptime_vm does real single-thread RMW. `examples/1701` (add/sub/
and/or/xor/min/max) green; unit test locks `atomicrmw add` + signed `min` vs unsigned `umin`.
Suite green (716/0).
**A.2a (CAS lock) — DONE**. `compare_exchange`/`_weak` wired end-to-end EXCEPT LLVM emission
(bails loudly; A.2b makes it real). New IR op `atomic_cmpxchg` + `AtomicCmpxchg{ptr, cmp, new,
val_ty, success_ordering, failure_ordering, weak}`; result type = `?T` (null = success). print
arm; emit dispatch → `emitAtomicCmpxchg` (BAILS). comptime_vm arm implements real single-thread
CAS (read actual / compare / store-on-equal / build `?T`: success→none, failure→some(actual);
weak == strong at comptime). Recognizer extended (`atomic_cmpxchg`/`_weak`, 6 args) — CAS
restricted to INTEGER T (loud reject); BOTH orderings resolved via `atomicOrderingFromNode`;
dual-ordering validation (failure may not be release/acq_rel nor stronger than success, via
`atomicOrderingRank`). Methods `compare_exchange`/`_weak` on `Atomic($T)` with comptime
`$success`/`$failure: Ordering`. `examples/1702` locked to the bail; `examples/1186` locks the
rejected ordering pair (failure=.seq_cst > success=.relaxed). Suite green (718/0).
### A.1 (RMW) — DONE (A.1a lock + A.1b green)
`fetch_add/sub/and/or/xor` + `fetch_min/max` → LLVM `atomicrmw` (returns OLD value). New IR op
`atomic_rmw` + `RmwKind` (no `nand`); `LLVMBuildAtomicRMW` with binop from kind, signed/unsigned
`Min/Max` from `val_ty`. RMW restricted to INTEGER T (float fadd / pointer RMW out of scope,
rejected loudly); all five orderings valid for RMW. comptime_vm does real single-thread RMW.
`examples/1701` green; unit test locks `atomicrmw add` + signed `min` vs unsigned `umin`.
## Next step
**A.2 — CAS**: `compare_exchange`/`_weak` → LLVM `cmpxchg` (returns **`?T`, null = success**).
New IR op `atomic_cmpxchg` (ptr, cmp, new, success_ord, failure_ord, weak). Validate the two
orderings (failure may not be release/acq_rel nor stronger than success). `_weak` → `LLVMSetWeak`.
**A.2b — CAS green**: replace the `emitAtomicCmpxchg` bail with real `LLVMBuildAtomicCmpXchg`
(success/failure orderings; `LLVMSetWeak` for weak). Build the `?T` result: `extractvalue 1` =
success (i1); `has = xor(success, true)` (null = success); `insertvalue {actual, has}`. Green
`examples/1702`; unit test asserting `cmpxchg` + the weak marker.
### Earlier — A.0c (guard hardening)
Adversarial review of A.0 found two CRITICAL silent-wrong defects (raw LLVM verifier errors