atomics A.2a: CAS ops + recognizer + methods, emit bails (lock)
compare_exchange/_weak wired end-to-end except LLVM emission (bails loudly;
A.2b makes it real). New IR op atomic_cmpxchg + AtomicCmpxchg{ptr, cmp, new,
val_ty, success_ordering, failure_ordering, weak}; result type = ?T (null =
SUCCESS, failure carries the actual value for retry). print arm; emit dispatch
-> emitAtomicCmpxchg (BAILS). comptime_vm arm does real single-thread CAS (read
actual / compare / store-on-equal / build ?T: success->none, failure->some;
weak == strong at comptime). Recognizer extended (atomic_cmpxchg/_weak, 6 args)
-- CAS restricted to INTEGER T (loud reject); BOTH orderings resolved via
atomicOrderingFromNode; dual-ordering validation (failure may not be
release/acq_rel nor stronger than success, via atomicOrderingRank). Methods
compare_exchange/_weak on Atomic($T) with comptime $success/$failure: Ordering.
examples/1702 locked to the bail; examples/1186 locks a rejected ordering pair.
Suite green (718/0).
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@@ -18,6 +18,7 @@ const Store = ir_inst.Store;
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const AtomicLoad = ir_inst.AtomicLoad;
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const AtomicStore = ir_inst.AtomicStore;
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const AtomicRmw = ir_inst.AtomicRmw;
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const AtomicCmpxchg = ir_inst.AtomicCmpxchg;
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const Conversion = ir_inst.Conversion;
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const GlobalId = ir_inst.GlobalId;
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const GlobalSet = ir_inst.GlobalSet;
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@@ -425,6 +426,15 @@ pub const Ops = struct {
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}
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}
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// A.2a (Stream A) lock: emission BAILS LOUDLY until A.2b wires the real
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// LLVMBuildAtomicCmpXchg + the `?T` result (null = success).
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pub fn emitAtomicCmpxchg(self: Ops, instruction: *const Inst, a: AtomicCmpxchg) void {
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_ = a;
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std.debug.print("error: atomic compare-exchange LLVM emission not yet implemented (Stream A, A.2b)\n", .{});
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self.e.comptime_failed = true;
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self.e.mapRef(c.LLVMGetUndef(self.e.toLLVMType(if (instruction.ty == .void) .i64 else instruction.ty)));
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}
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pub fn emitAtomicStore(self: Ops, a: AtomicStore) void {
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const ptr = self.e.resolveRef(a.ptr);
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var val = self.e.resolveRef(a.val);
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