ir

src/main.zig

@@ -91,6 +91,8 @@ pub fn main(init: std.process.Init) !void {
         std.debug.print("compiled: {s}\n", .{output_name});
     } else if (std.mem.eql(u8, command, "ir")) {
         emitIR(allocator, io, path, target_config) catch return;
+    } else if (std.mem.eql(u8, command, "ir-dump")) {
+        dumpSxIR(allocator, io, path) catch return;
     } else if (std.mem.eql(u8, command, "asm")) {
         emitAsm(allocator, io, path, target_config) catch return;
     } else if (std.mem.eql(u8, command, "run")) {
@@ -304,6 +306,24 @@ fn compilePipeline(allocator: std.mem.Allocator, io: std.Io, input_path: []const
     return comp;
 }
 
+fn dumpSxIR(allocator: std.mem.Allocator, io: std.Io, input_path: []const u8) !void {
+    const source = try readSource(allocator, io, input_path);
+    var comp = sx.core.Compilation.init(allocator, io, input_path, source, .{});
+    defer comp.deinit();
+
+    comp.parse() catch { comp.renderErrors(); return error.CompileError; };
+    comp.resolveImports() catch { comp.renderErrors(); return error.CompileError; };
+
+    var ir_module = comp.lowerToIR();
+    defer ir_module.deinit();
+
+    var aw = std.Io.Writer.Allocating.init(allocator);
+    sx.ir.printModule(&ir_module, &aw.writer) catch return;
+    var result = aw.writer.toArrayList();
+    defer result.deinit(allocator);
+    std.debug.print("{s}", .{result.items});
+}
+
 fn emitIR(allocator: std.mem.Allocator, io: std.Io, input_path: []const u8, target_config: sx.codegen.TargetConfig) !void {
     var timer = Timing.init(false);
     var comp = try compilePipeline(allocator, io, input_path, target_config, &timer);