4128416d48
Implements read-write (`+r` / `+{reg}`) `-> @place` outputs. LLVM has
no `+` constraint, so a read-write place lowers to:
- an output `=` constraint (return slot, stored back through the
place after the call), with the leading `+` rewritten to `=`; plus
- a TIED input constraint (the decimal index of that output) appended
after the regular inputs, seeded with the place's loaded value
passed as a call arg.
Tied inputs are appended last so existing operand indices (%[name] ->
${N}) are undisturbed; asmOperandIndex stays correct. Lowering no longer
rejects `+` (indirect `*` still rejected). emitInlineAsm grows the
arg/param arrays by the rw count, loads each seed, and emits the tied
constraint.
Verified by running: increment-in-place (41 -> 42) and a mixed case
(rw place + regular input + value output) producing the textbook
"=r,=r,r,0" constraint with correct ${N} indices. 1650 flipped from
the rejection lock to a runnable aarch64-pinned example (ir-only
elsewhere). zig build test green (658 corpus, 446 unit).
21 lines
508 B
Plaintext
21 lines
508 B
Plaintext
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; Function Attrs: nounwind
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define internal i64 @compute() #0 {
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entry:
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%alloca = alloca i64, align 8
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store i64 41, ptr %alloca, align 8
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%asm.rw.seed = load i64, ptr %alloca, align 8
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%asm = call i64 asm sideeffect "add ${0}, ${0}, #1", "=r,0"(i64 %asm.rw.seed)
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store i64 %asm, ptr %alloca, align 8
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%load = load i64, ptr %alloca, align 8
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ret i64 %load
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}
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%call = call i64 @compute()
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%ca.tr = trunc i64 %call to i32
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ret i32 %ca.tr
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}
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