17e3b91eb9
Adds ir-only x86_64 examples mirroring the aarch64 feature examples, so
each emit path is locked on both arches:
- 1657 read-write `+` → "incq ${0}", "=r,0" (tied input)
- 1658 indirect `=*m` → "movq $$42, ${0}", "=*m"(ptr elementtype i64)
- 1659 symbol `"s"` → "call ${2:P}", direct call to an exported sx fn
Each is x86-pinned (ir-only on this aarch64 host — the .ir is the
assertion; runs on x86_64-linux, main returns 0 on success / 1 if the
asm misbehaved). x86 templates validated by cross-emitting an object
(LLVM's integrated assembler accepts them; objdump confirms 1659 is a
direct `call` reloc to cb). Note: x86 direct calls need the `P` operand
modifier (`%[fn:P]`); aarch64 `bl %[fn]` needs none. Pure additive
locks, no compiler change. zig build test green (668 corpus, 446 unit).
25 lines
608 B
Plaintext
25 lines
608 B
Plaintext
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; Function Attrs: nounwind
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define internal i64 @poke() #0 {
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entry:
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%alloca = alloca i64, align 8
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store i64 0, ptr %alloca, align 8
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call void asm sideeffect "movq $$42, ${0}", "=*m"(ptr elementtype(i64) %alloca)
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%load = load i64, ptr %alloca, align 8
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ret i64 %load
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}
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%call = call i64 @poke()
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%icmp = icmp ne i64 %call, 42
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br i1 %icmp, label %if.then.0, label %if.merge.1
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if.then.0: ; preds = %entry
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ret i32 1
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if.merge.1: ; preds = %entry
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ret i32 0
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}
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