Surface rename of the signed integer family: s1..s64 become i1..i64
(u1..u64, usize, isize unchanged). 'string' keeps the s-prefix arm in
name classification; width parsing moves to the i-prefix arm next to
isize.
Internal TypeId tags follow the surface (.s8/.s16/.s32/.s64 ->
.i8/.i16/.i32/.i64), as do mono-key mangle fragments (ptr_i64,
tu_i64_bool) and all display/diagnostic formatting (i{d}).
Migrated in the same sweep: stdlib + examples + issue repros + FFI C
companions (shared symbol names like ffi_id_i64), expected
stdout/stderr/ir snapshots, specs.md, readme.md, CLAUDE.md/AGENTS.md,
implementation_plan.md, docs/, issue writeups. Vendored stb_image and
historical flow state left untouched.
zig build test: 426/426; examples suite: 595/595.
167 lines
3.9 KiB
Plaintext
167 lines
3.9 KiB
Plaintext
#import "modules/std.sx";
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#import "modules/math";
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#import "modules/build.sx";
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#import "modules/std/test.sx";
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pkg :: #import "tests/fixtures/testpkg";
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add :: (a: i32, b: i32) -> i32 { a + b }
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mul :: (a: i32, b: i32) -> i32 { a * b }
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// P4 edge: Chained default→default calls
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Chained :: protocol {
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base :: (msg: string) -> i32;
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wrap :: (msg: string) -> i32 {
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self.base(msg) + 1
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}
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double_wrap :: (msg: string) -> i32 {
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self.wrap(msg) + self.wrap(msg)
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}
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}
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main :: () {
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// ========================================================
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// 2. OPERATORS & PRECEDENCE
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// ========================================================
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print("=== 2. Operators ===\n");
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// Arithmetic
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print("add: {}\n", 3 + 4);
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print("sub: {}\n", 10 - 3);
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print("mul: {}\n", 6 * 7);
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print("div: {}\n", 20 / 4);
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print("mod: {}\n", 17 % 5);
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print("neg: {}\n", -(5));
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// Comparisons
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print("eq: {}\n", 5 == 5);
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print("neq: {}\n", 5 != 3);
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print("lt: {}\n", 3 < 5);
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print("gt: {}\n", 5 > 3);
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print("le: {}\n", 5 <= 5);
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print("ge: {}\n", 5 >= 3);
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// Chained comparisons
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v := 50;
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print("chain: {}\n", 0 <= v <= 100);
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print("chain-gt: {}\n", 100 > v > 0);
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print("chain-mixed: {}\n", 100 > v >= 0);
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// Equality chains
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print("eq-chain: {}\n", 5 == 5 == 5);
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print("eq-chain-f: {}\n", 5 == 5 == 6);
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// Bitwise
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print("band: {}\n", 0xFF & 0x0F);
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print("bor: {}\n", 1 | 2 | 4);
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// Bitwise XOR
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print("bxor: {}\n", 0xFF ^ 0x0F);
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print("bxor2: {}\n", 6 ^ 3);
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// Bitwise NOT
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print("bnot: {}\n", ~0);
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print("bnot2: {}\n", ~1);
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// Shifts
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print("shl: {}\n", 1 << 4);
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print("shr: {}\n", 256 >> 4);
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print("shl2: {}\n", 3 << 3);
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print("shr2: {}\n", 255 >> 1);
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// Bitwise on variables
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bv1 := 0xFF;
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bv2 := 0x0F;
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print("band-var: {}\n", bv1 & bv2);
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bv3 := 1;
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bv4 := 6;
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print("bor-var: {}\n", bv3 | bv4);
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print("bxor-var: {}\n", bv1 ^ bv2);
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print("shl-var: {}\n", bv3 << 4);
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print("shr-var: {}\n", bv1 >> 4);
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print("bnot-var: {}\n", ~bv2);
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// Bitwise compound assignment
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bca := 0xFF;
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bca &= 0x0F;
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print("and-assign: {}\n", bca);
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bco := 0x0F;
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bco |= 0xF0;
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print("or-assign: {}\n", bco);
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bcx := 0xFF;
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bcx ^= 0x0F;
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print("xor-assign: {}\n", bcx);
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bcs := 1;
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bcs <<= 8;
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print("shl-assign: {}\n", bcs);
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bcr := 256;
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bcr >>= 4;
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print("shr-assign: {}\n", bcr);
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// Modulo on variables
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mv1 := 17;
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mv2 := 5;
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print("mod-var: {}\n", mv1 % mv2);
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// Logical (short-circuit)
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print("and: {}\n", true and true);
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print("and-false: {}\n", true and false);
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print("or: {}\n", false or true);
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print("or-false: {}\n", false or false);
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// Short-circuit verification
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print("short-and: {}\n", false and true);
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print("short-or: {}\n", true or false);
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// Compound assignment
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ca := 10;
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ca += 5;
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print("ca+=: {}\n", ca);
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ca -= 3;
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print("ca-=: {}\n", ca);
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ca *= 2;
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print("ca*=: {}\n", ca);
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ca /= 6;
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print("ca/=: {}\n", ca);
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// Precedence
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print("prec1: {}\n", 2 + 3 * 4);
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print("prec2: {}\n", (2 + 3) * 4);
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// xx explicit cast
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big2 : f64 = 200.7;
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small : u8 = xx big2;
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print("xx-cast: {}\n", small);
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// Implicit widening conversions
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wu : u8 = 200;
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ws : i64 = wu;
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print("widen-u8-i64: {}\n", ws);
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wi3 : i32 = 42;
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wf : f64 = wi3;
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print("widen-i32-f64: {}\n", wf);
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wf32 : f32 = 1.5;
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wf64 : f64 = wf32;
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print("widen-f32-f64: {}\n", wf64);
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wu2 : u8 = 100;
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ws2 : i16 = wu2;
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print("widen-u8-i16: {}\n", ws2);
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// More xx narrowing
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xl : i64 = 12345;
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xs : i32 = xx xl;
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print("xx-i64-i32: {}\n", xs);
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xd : f64 = 1.5;
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xf : f32 = xx xd;
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print("xx-f64-f32: {}\n", xf);
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xdf : f64 = 7.9;
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xdi : i32 = xx xdf;
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print("xx-f64-i32: {}\n", xdi);
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}
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