dd363ca877
First implementation step of Stream B1 (fibers). Make the inert abi(.pure) ABI carry an is_pure flag through lowering, with LLVM emission deliberately bailing loudly until B1.0b — the lock half of the lock->green cadence. - IR Function.is_pure, set from fd.abi == .pure at both declareFunction decl sites. - funcWantsImplicitCtx skips .pure (no synthetic __sx_ctx, mirroring the .c skip): a pure fn reads args from ABI registers, an implicit ctx would occupy a register slot the asm doesn't expect. - both body-lowering paths bypass lowerValueBody for .pure: lower the asm body as statements + cap with unreachable. A pure body has no sx return (the asm rets itself), so the implicit-return diagnostic must not fire. - emit_llvm Pass 2 bails loudly when func.is_pure (build-gating nonzero exit) rather than emit a framed body, whose epilogue would corrupt a context switch's deliberate SP-in != SP-out. examples/1800-concurrency-pure-asm.sx: one host example (no .build pin -- the bail fires before instruction selection, so it is host-independent), locked to the bail snapshot. B1.0b flips emit to LLVM's naked attribute + asm-only body and pins the example per-arch. The sx-facing name is "pure" throughout (field, diagnostic); LLVM's naked attribute is only the B1.0b lowering mechanism. Suite green (722/0).
25 lines
1.1 KiB
Plaintext
25 lines
1.1 KiB
Plaintext
// Stream B1 (fibers) step B1.0a — LOCK commit for `abi(.pure)`.
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//
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// An `abi(.pure)` function has no calling-convention prologue/epilogue/frame
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// and no implicit `__sx_ctx`: its body is a single asm block that sets the
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// return register and emits its own `ret`. This is the substrate the per-arch
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// fiber context-switch is built on (design §4.6) — a `.c` epilogue would
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// restore SP from the wrong stack across a switch (SP-in ≠ SP-out by design).
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//
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// This commit only plumbs the `is_pure` flag through lowering; LLVM emission
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// (the `naked` attribute + asm-only body) is NOT implemented yet, so emit bails
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// LOUDLY (build-gating, nonzero exit) rather than emit a framed body. The bail
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// is at the function level, before any asm/instruction selection, so it is
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// host-independent (no `.build` target pin needed until B1.0b adds emission).
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// B1.0b flips this to a green, aarch64-pinned end-to-end run.
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answer :: () -> i64 abi(.pure) {
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asm volatile {
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#string ASM
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mov x0, #42
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ret
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ASM
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};
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}
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main :: () -> i64 { return answer(); }
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