718f27e27f
fetch_add/sub/and/or/xor/min/max wired end-to-end except LLVM emission (bails
loudly; A.1b makes it real). New IR op atomic_rmw + RmwKind (no nand) +
AtomicRmw{ptr, operand, val_ty, ordering, kind}. print arm; comptime_vm arm
implements real single-thread RMW (load/compute/store/return-old, signed|unsigned
min/max from val_ty). Recognizer extended (rmwKindFromName) — RMW restricted to
integer T (float fadd / pointer RMW out of scope, rejected loudly); all orderings
valid for RMW. Methods fetch_* on Atomic($T) with comptime $o: Ordering.
examples/1701 locked to the bail. Suite green (716/0).
23 lines
1.1 KiB
Plaintext
23 lines
1.1 KiB
Plaintext
// Atomic($T) read-modify-write: fetch_add/sub/and/or/xor/min/max → LLVM atomicrmw.
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// Each returns the OLD value. Stream A (atomics) A.1. Single-thread.
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#import "modules/std.sx";
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#import "modules/std/atomic.sx";
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main :: () {
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a := Atomic(i64).init(10);
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print("old add: {}\n", a.fetch_add(5, .seq_cst)); // returns 10, now 15
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print("old sub: {}\n", a.fetch_sub(3, .acq_rel)); // returns 15, now 12
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print("now: {}\n", a.load(.acquire)); // 12
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b := Atomic(i64).init(0xF0);
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print("old and: {}\n", b.fetch_and(0x3C, .relaxed));// returns 0xF0(240), now 0x30(48)
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print("old or: {}\n", b.fetch_or(0x03, .relaxed)); // returns 0x30(48), now 0x33(51)
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print("old xor: {}\n", b.fetch_xor(0x0F, .relaxed));// returns 0x33(51), now 0x3C(60)
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print("now: {}\n", b.load(.relaxed)); // 60
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m := Atomic(i64).init(20);
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print("old min: {}\n", m.fetch_min(8, .seq_cst)); // returns 20, now 8
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print("old max: {}\n", m.fetch_max(15, .seq_cst)); // returns 8, now 15
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print("now: {}\n", m.load(.seq_cst)); // 15
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}
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