dca396ed1f
compare_exchange/_weak wired end-to-end except LLVM emission (bails loudly;
A.2b makes it real). New IR op atomic_cmpxchg + AtomicCmpxchg{ptr, cmp, new,
val_ty, success_ordering, failure_ordering, weak}; result type = ?T (null =
SUCCESS, failure carries the actual value for retry). print arm; emit dispatch
-> emitAtomicCmpxchg (BAILS). comptime_vm arm does real single-thread CAS (read
actual / compare / store-on-equal / build ?T: success->none, failure->some;
weak == strong at comptime). Recognizer extended (atomic_cmpxchg/_weak, 6 args)
-- CAS restricted to INTEGER T (loud reject); BOTH orderings resolved via
atomicOrderingFromNode; dual-ordering validation (failure may not be
release/acq_rel nor stronger than success, via atomicOrderingRank). Methods
compare_exchange/_weak on Atomic($T) with comptime $success/$failure: Ordering.
examples/1702 locked to the bail; examples/1186 locks a rejected ordering pair.
Suite green (718/0).
12 lines
437 B
Plaintext
12 lines
437 B
Plaintext
// Atomic compare-exchange dual-ordering validation: the FAILURE ordering may not
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// be stronger than the SUCCESS ordering (LLVM rule). Here failure=.seq_cst (rank
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// 3) is stronger than success=.relaxed (rank 0) → loud diagnostic, not invalid IR.
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// Stream A (atomics) A.2.
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#import "modules/std.sx";
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#import "modules/std/atomic.sx";
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main :: () {
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a := Atomic(i64).init(0);
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_ := a.compare_exchange(0, 1, .relaxed, .seq_cst);
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}
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