fca4304f83
swap (atomicrmw xchg) and a standalone fence wired end-to-end except LLVM emission (both bail loudly; A.3b makes them real). - RmwKind += xchg; atomic_swap intrinsic + swap method reuse the atomic_rmw op. - new atomic_fence op (+ AtomicFence) — ordering-only, void; fence($o)/atomic_fence intrinsic; recognizer rejects .relaxed (LLVM has no monotonic fence). - comptime_vm: xchg = store operand/return old; fence = no-op (single-thread). - examples 1703 (swap) + 1704 (fence) locked to bails; 1187 (relaxed-fence reject). - 1186 converted to a direct-intrinsic call → stable user-file diagnostic span (the lib-forward-site span shifted when atomic.sx grew — fragile-snapshot fix). Also fixes a latent A.2 comptime-CAS bug found while here: the success/null has_value write was 'writeWord(addr, SIZE=0, val=1)' — a 0-byte no-op, correct ONLY because allocBytes zero-inits (REJECTED-PATTERNS 'coincidentally correct'). Now writes the flag explicitly (size=1, val=0). Suite green (721/0).
16 lines
486 B
Plaintext
16 lines
486 B
Plaintext
// Standalone memory fence — fence(.ordering) → LLVM fence. Stream A (atomics) A.3.
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// (.relaxed is rejected; see 1187.) Single-thread: a fence is observable only as
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// "compiled + ran without error" here.
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#import "modules/std.sx";
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#import "modules/std/atomic.sx";
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main :: () {
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a := Atomic(i64).init(1);
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a.store(2, .relaxed);
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fence(.release);
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a.store(3, .relaxed);
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fence(.acquire);
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fence(.seq_cst);
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print("after fences: {}\n", a.load(.relaxed)); // 3
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}
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