6c08de8ec1
Adds the `inline_asm: InlineAsm` opcode to the IR Op union (inst.zig): interned template + operand list (role/name/constraint/operand) + interned clobber names + has_side_effects; the result rides on Inst.ty (void / scalar / tuple). The new variant forces coverage in the exhaustive Op switches: - interp.zig: loud bailDetail — inline asm is never comptime-evaluable. - print.zig: an IR-dump arm. - emit_llvm.zig: a @panic TRIPWIRE — emit lands in Phase D, and until then lowerAsmExpr still bails, so no inline_asm op is ever created. Reaching emit would mean lowering switched over before emit was ready; crash loudly rather than miscompile. No behavior change: lowering still bails, the op is constructed only in the new `inline_asm op shape` unit test (inst.test.zig). zig build test green (652 corpus, 446 unit).
99 lines
3.4 KiB
Zig
99 lines
3.4 KiB
Zig
// Tests for inst.zig
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const std = @import("std");
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const types = @import("types.zig");
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const inst_mod = @import("inst.zig");
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const Ref = inst_mod.Ref;
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const BlockId = inst_mod.BlockId;
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const FuncId = inst_mod.FuncId;
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const Inst = inst_mod.Inst;
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const Block = inst_mod.Block;
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const Function = inst_mod.Function;
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const InlineAsm = inst_mod.InlineAsm;
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const StringId = types.StringId;
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test "Ref none sentinel" {
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try std.testing.expect(Ref.none.isNone());
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try std.testing.expect(!Ref.fromIndex(0).isNone());
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}
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test "basic instruction creation" {
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const inst = Inst{
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.op = .{ .add = .{ .lhs = Ref.fromIndex(0), .rhs = Ref.fromIndex(1) } },
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.ty = .i32,
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};
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try std.testing.expectEqual(types.TypeId.i32, inst.ty);
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switch (inst.op) {
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.add => |bin| {
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try std.testing.expectEqual(Ref.fromIndex(0), bin.lhs);
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try std.testing.expectEqual(Ref.fromIndex(1), bin.rhs);
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},
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else => unreachable,
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}
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}
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test "block creation" {
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const alloc = std.testing.allocator;
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var block = Block.init(@enumFromInt(1), &.{});
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defer block.deinit(alloc);
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block.insts.append(alloc, .{
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.op = .{ .const_int = 42 },
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.ty = .i64,
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}) catch unreachable;
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block.insts.append(alloc, .{
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.op = .{ .ret = .{ .operand = Ref.fromIndex(0) } },
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.ty = .i64,
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}) catch unreachable;
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try std.testing.expectEqual(@as(usize, 2), block.insts.items.len);
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}
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test "inline_asm op shape (ASM stream Phase C.0)" {
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// out_value (yields the value, operand = .none) + a named-less input,
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// plus two clobbers; result rides on Inst.ty.
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const operands = [_]InlineAsm.AsmOperand{
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.{ .role = .out_value, .name = @enumFromInt(1), .constraint = @enumFromInt(2), .operand = Ref.none },
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.{ .role = .input, .name = .empty, .constraint = @enumFromInt(3), .operand = Ref.fromIndex(5) },
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};
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const clobbers = [_]StringId{ @enumFromInt(4), @enumFromInt(6) };
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const inst = Inst{
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.op = .{ .inline_asm = .{
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.template = @enumFromInt(10),
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.operands = &operands,
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.clobbers = &clobbers,
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.has_side_effects = true,
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} },
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.ty = .i64,
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};
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switch (inst.op) {
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.inline_asm => |a| {
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try std.testing.expect(a.has_side_effects);
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try std.testing.expectEqual(@as(usize, 2), a.operands.len);
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try std.testing.expectEqual(@as(usize, 2), a.clobbers.len);
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try std.testing.expectEqual(InlineAsm.AsmOperand.Role.out_value, a.operands[0].role);
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// an out_value operand carries no input Ref — the asm yields it
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try std.testing.expect(a.operands[0].operand.isNone());
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try std.testing.expectEqual(InlineAsm.AsmOperand.Role.input, a.operands[1].role);
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try std.testing.expectEqual(Ref.fromIndex(5), a.operands[1].operand);
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// an anonymous operand uses the `.empty` StringId sentinel
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try std.testing.expectEqual(StringId.empty, a.operands[1].name);
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},
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else => unreachable,
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}
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}
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test "function creation" {
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const alloc = std.testing.allocator;
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const params = &[_]Function.Param{
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.{ .name = @enumFromInt(1), .ty = .i32 },
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.{ .name = @enumFromInt(2), .ty = .i32 },
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};
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var func = Function.init(@enumFromInt(3), params, .i64);
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defer func.deinit(alloc);
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try std.testing.expectEqual(types.TypeId.i64, func.ret);
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try std.testing.expectEqual(@as(usize, 2), func.params.len);
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}
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