d3c6ffed5a
Replaces the N>1 "Phase E" bail with a shared asmResultType helper (lowering +
inferType) that derives the result type from the out_value operands: 0→void,
1→T, N→a named tuple (fields named via the §II.5 effective-name rule).
Key realization: toLLVMType(tuple) already produces a literal struct {T1,…,Tn} —
exactly what LLVM's multi-output inline asm returns — so emit needs NO change.
Building the op with a tuple result type makes the asm call return the struct,
which IS sx's tuple value (destructured by the normal tuple_get path).
inferType's .asm_expr arm now also delegates to asmResultType (single owner), so
`return asm`, `x := asm`, and `q, r := asm` all agree on the type.
Verified end-to-end on aarch64: split(0x1234)→(lo=52,hi=18), a udiv/msub
divmod→(3,2). IR: `call { i64, i64 } asm "divq ${4}",
"={rax},={rdx},{rax},{rdx},r,~{cc}"(…)` → extractvalue → tuple.
1640 → the x86_64 multi-output IR lock (ir-only); 1647 → a multi-output example
that runs on aarch64.
zig build test green (655 corpus, 446 unit).
32 lines
1.0 KiB
Plaintext
32 lines
1.0 KiB
Plaintext
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; Function Attrs: nounwind
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define internal { i64, i64 } @split(i64 %0) #0 {
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entry:
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%alloca = alloca i64, align 8
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store i64 %0, ptr %alloca, align 8
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%load = load i64, ptr %alloca, align 8
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%asm = call { i64, i64 } asm " and ${0}, ${2}, #0xff\0A lsr ${1}, ${2}, #8\0A", "=r,=r,r"(i64 %load)
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%tg = extractvalue { i64, i64 } %asm, 0
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%tgN = extractvalue { i64, i64 } %asm, 1
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%ti = insertvalue { i64, i64 } undef, i64 %tg, 0
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%tiN = insertvalue { i64, i64 } %ti, i64 %tgN, 1
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ret { i64, i64 } %tiN
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}
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%call = call { i64, i64 } @split(i64 4660)
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%tg = extractvalue { i64, i64 } %call, 0
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%alloca = alloca i64, align 8
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store i64 %tg, ptr %alloca, align 8
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%tgN = extractvalue { i64, i64 } %call, 1
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%allocaN = alloca i64, align 8
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store i64 %tgN, ptr %allocaN, align 8
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%load = load i64, ptr %alloca, align 8
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%loadN = load i64, ptr %allocaN, align 8
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%add = add i64 %load, %loadN
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%ca.tr = trunc i64 %add to i32
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ret i32 %ca.tr
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}
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