d8076b9333
Surface rename of the signed integer family: s1..s64 become i1..i64
(u1..u64, usize, isize unchanged). 'string' keeps the s-prefix arm in
name classification; width parsing moves to the i-prefix arm next to
isize.
Internal TypeId tags follow the surface (.s8/.s16/.s32/.s64 ->
.i8/.i16/.i32/.i64), as do mono-key mangle fragments (ptr_i64,
tu_i64_bool) and all display/diagnostic formatting (i{d}).
Migrated in the same sweep: stdlib + examples + issue repros + FFI C
companions (shared symbol names like ffi_id_i64), expected
stdout/stderr/ir snapshots, specs.md, readme.md, CLAUDE.md/AGENTS.md,
implementation_plan.md, docs/, issue writeups. Vendored stb_image and
historical flow state left untouched.
zig build test: 426/426; examples suite: 595/595.
41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
// Regression for issue 0057: a match (`if subject == { case ... }`) whose arms
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// ALL diverge (each `return`s) used to fail LLVM verification (a `void` phi +
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// "terminator in the middle of a basic block") — lowerMatch emitted a
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// value-merge phi and a fallback `const` into arm blocks that had already
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// terminated. Now a fully-diverging match produces no merge phi, and a mixed
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// match (some arms diverge, some yield values) materializes the merge only
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// from the value-producing arms.
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#import "modules/std.sx";
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// All arms diverge — the match is `noreturn`, no merge phi.
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classify :: (n: i32) -> i32 {
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if n == {
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case 0: return 10;
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case 1: return 20;
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else: return 90;
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}
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return 0; // unreachable
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}
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// Mixed: value arms + a diverging arm.
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pick :: (n: i32) -> i32 {
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v := if n == {
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case 0: 1;
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case 1: return 100; // diverging arm — no fallback const after its `ret`
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else: 3;
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};
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return v + 5;
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}
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main :: () -> i32 {
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r : i32 = 0;
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r = r + classify(0); // 10
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r = r + classify(1); // 20
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r = r + classify(7); // 90
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r = r + pick(0); // 1 + 5 = 6
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r = r + pick(9); // 3 + 5 = 8 (else arm)
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print("match result: {}\n", r); // 10+20+90+6+8 = 134
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return r;
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}
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