atomics A.3a: swap + fence ops + recognizer, emit bails (lock)

swap (atomicrmw xchg) and a standalone fence wired end-to-end except LLVM
emission (both bail loudly; A.3b makes them real).
- RmwKind += xchg; atomic_swap intrinsic + swap method reuse the atomic_rmw op.
- new atomic_fence op (+ AtomicFence) — ordering-only, void; fence($o)/atomic_fence
  intrinsic; recognizer rejects .relaxed (LLVM has no monotonic fence).
- comptime_vm: xchg = store operand/return old; fence = no-op (single-thread).
- examples 1703 (swap) + 1704 (fence) locked to bails; 1187 (relaxed-fence reject).
- 1186 converted to a direct-intrinsic call → stable user-file diagnostic span
  (the lib-forward-site span shifted when atomic.sx grew — fragile-snapshot fix).

Also fixes a latent A.2 comptime-CAS bug found while here: the success/null
has_value write was 'writeWord(addr, SIZE=0, val=1)' — a 0-byte no-op, correct
ONLY because allocBytes zero-inits (REJECTED-PATTERNS 'coincidentally correct').
Now writes the flag explicitly (size=1, val=0). Suite green (721/0).

examples/1186-diagnostics-atomic-cas-ordering.sx

@@ -1,11 +1,12 @@
 // Atomic compare-exchange dual-ordering validation: the FAILURE ordering may not
 // be stronger than the SUCCESS ordering (LLVM rule). Here failure=.seq_cst (rank
 // 3) is stronger than success=.relaxed (rank 0) → loud diagnostic, not invalid IR.
-// Stream A (atomics) A.2.
+// Calls the intrinsic directly so the diagnostic span is stable (user file, not
+// the lib forward site). Stream A (atomics) A.2.
 #import "modules/std.sx";
 #import "modules/std/atomic.sx";
 
 main :: () {
-    a := Atomic(i64).init(0);
-    _ := a.compare_exchange(0, 1, .relaxed, .seq_cst);
+    n : i64 = 0;
+    _ := atomic_cmpxchg(i64, @n, 0, 1, .relaxed, .seq_cst);
 }