atomics A.3a: swap + fence ops + recognizer, emit bails (lock)

swap (atomicrmw xchg) and a standalone fence wired end-to-end except LLVM
emission (both bail loudly; A.3b makes them real).
- RmwKind += xchg; atomic_swap intrinsic + swap method reuse the atomic_rmw op.
- new atomic_fence op (+ AtomicFence) — ordering-only, void; fence($o)/atomic_fence
  intrinsic; recognizer rejects .relaxed (LLVM has no monotonic fence).
- comptime_vm: xchg = store operand/return old; fence = no-op (single-thread).
- examples 1703 (swap) + 1704 (fence) locked to bails; 1187 (relaxed-fence reject).
- 1186 converted to a direct-intrinsic call → stable user-file diagnostic span
  (the lib-forward-site span shifted when atomic.sx grew — fragile-snapshot fix).

Also fixes a latent A.2 comptime-CAS bug found while here: the success/null
has_value write was 'writeWord(addr, SIZE=0, val=1)' — a 0-byte no-op, correct
ONLY because allocBytes zero-inits (REJECTED-PATTERNS 'coincidentally correct').
Now writes the flag explicitly (size=1, val=0). Suite green (721/0).

src/ir/comptime_vm.zig

@@ -711,6 +711,7 @@ pub const Vm = struct {
                         const sp: i64 = @bitCast(operand);
                         break :blk @bitCast(if (want_max) @max(so, sp) else @min(so, sp));
                     },
+                    .xchg => operand, // swap: new value IS the operand
                 };
                 try self.writeField(table, frame.get(a.ptr.index()), vty, new_val);
                 return .{ .value = old };
@@ -733,14 +734,21 @@ pub const Vm = struct {
                 // Build the `?T` result in VM memory.
                 const opt_ty = ins.ty; // ?T
                 const addr = self.machine.allocBytes(table.typeSizeBytes(opt_ty), table.typeAlignBytes(opt_ty));
+                // writeWord(addr, SIZE, val): write the 1-byte has_value flag
+                // EXPLICITLY (size=1) — never rely on alloc zero-init for the
+                // success/null case (a size=0 write is a no-op, correct only by
+                // accident; REJECTED-PATTERNS "coincidentally correct").
+                const has_value_off = addr + table.typeSizeBytes(elem_ty);
                 if (success) {
-                    try self.machine.writeWord(addr + table.typeSizeBytes(elem_ty), 0, 1); // has_value = 0 (null)
+                    try self.machine.writeWord(has_value_off, 1, 0); // has_value = 0 (null)
                 } else {
                     try self.writeField(table, addr, elem_ty, actual); // payload = actual
-                    try self.machine.writeWord(addr + table.typeSizeBytes(elem_ty), 1, 1); // has_value = 1
+                    try self.machine.writeWord(has_value_off, 1, 1); // has_value = 1
                 }
                 return .{ .value = addr };
             },
+            // A fence is a no-op at comptime (single-thread → nothing to order).
+            .atomic_fence => return .{ .value = 0 },
             .struct_init => |agg| {
                 const table = try self.requireTable();
                 const sty = ins.ty;

src/ir/emit_llvm.zig

@@ -1569,6 +1569,7 @@ pub const LLVMEmitter = struct {
             .atomic_store => |a| self.ops().emitAtomicStore(a),
             .atomic_rmw => |a| self.ops().emitAtomicRmw(instruction, a),
             .atomic_cmpxchg => |a| self.ops().emitAtomicCmpxchg(instruction, a),
+            .atomic_fence => |a| self.ops().emitAtomicFence(a),
             // ── Globals ───────────────────────────────────────────
             .global_get => |gid| self.ops().emitGlobalGet(instruction, gid),
             .global_addr => |gid| self.ops().emitGlobalAddr(gid),

src/ir/inst.zig

@@ -166,6 +166,7 @@ pub const Op = union(enum) {
     atomic_store: AtomicStore, // atomic store to pointer with memory ordering
     atomic_rmw: AtomicRmw, // atomic read-modify-write; result is the OLD value
     atomic_cmpxchg: AtomicCmpxchg, // atomic compare-exchange; result is ?T (null = success)
+    atomic_fence: AtomicFence, // standalone memory fence; void result
 
     // ── Struct ops ──────────────────────────────────────────────────
     struct_init: Aggregate, // construct struct from field values
@@ -324,7 +325,7 @@ pub const AtomicStore = struct {
 /// Atomic read-modify-write operation kind. `min`/`max` pick the signed vs
 /// unsigned LLVM op (`Min`/`Max` vs `UMin`/`UMax`) from the value type's
 /// signedness at emit time. No `nand` (deliberately omitted).
-pub const RmwKind = enum { add, sub, @"and", @"or", xor, min, max };
+pub const RmwKind = enum { add, sub, @"and", @"or", xor, min, max, xchg };
 
 pub const AtomicRmw = struct {
     ptr: Ref,
@@ -351,6 +352,12 @@ pub const AtomicCmpxchg = struct {
     weak: bool,
 };
 
+/// Standalone memory fence (`fence(.seq_cst)`) — no address, void result. The
+/// ordering may NOT be `relaxed` (LLVM has no monotonic/unordered fence).
+pub const AtomicFence = struct {
+    ordering: AtomicOrdering,
+};
+
 pub const Conversion = struct {
     operand: Ref,
     from: TypeId,

src/ir/lower/call.zig

@@ -1723,6 +1723,25 @@ fn atomicOrderingFromNode(self: *Lowering, node: *const Node) ?inst_mod.AtomicOr
 /// scalar of size 1/2/4/8/16. Both constraints are loud diagnostics, never silent
 /// defaults. Returns null if `name` is not an atomic intrinsic.
 pub fn tryLowerAtomicIntrinsic(self: *Lowering, name: []const u8, c: *const ast.Call) ?Ref {
+    // Fence is a standalone op — ordering only, no `$T`/ptr (different shape).
+    if (std.mem.eql(u8, name, "atomic_fence")) {
+        if (c.args.len != 1) {
+            if (self.diagnostics) |d| d.addFmt(.err, c.callee.span, "atomic_fence expects 1 argument", .{});
+            return Ref.none;
+        }
+        const ordering = atomicOrderingFromNode(self, c.args[0]) orelse {
+            if (self.diagnostics) |d| d.addFmt(.err, c.args[0].span, "fence ordering must be a constant ordering literal", .{});
+            return Ref.none;
+        };
+        // LLVM has no monotonic/unordered fence — `.relaxed` is invalid.
+        if (ordering == .relaxed) {
+            if (self.diagnostics) |d| d.addFmt(.err, c.args[0].span, "fence ordering cannot be .relaxed (use .acquire / .release / .acq_rel / .seq_cst)", .{});
+            return Ref.none;
+        }
+        self.builder.emitVoid(.{ .atomic_fence = .{ .ordering = ordering } }, .void);
+        return Ref.none; // fence has a void result
+    }
+
     const is_load = std.mem.eql(u8, name, "atomic_load");
     const is_store = std.mem.eql(u8, name, "atomic_store");
     const rmw_kind = rmwKindFromName(name); // atomic_fetch_add/sub/and/or/xor/min/max
@@ -1875,6 +1894,7 @@ fn rmwKindFromName(name: []const u8) ?inst_mod.RmwKind {
     if (std.mem.eql(u8, name, "atomic_fetch_xor")) return .xor;
     if (std.mem.eql(u8, name, "atomic_fetch_min")) return .min;
     if (std.mem.eql(u8, name, "atomic_fetch_max")) return .max;
+    if (std.mem.eql(u8, name, "atomic_swap")) return .xchg; // swap = exchange RMW
     return null;
 }
 

src/ir/print.zig

@@ -240,6 +240,10 @@ fn printInst(instruction: *const Inst, ref_idx: u32, tt: *const TypeTable, write
         },
         .atomic_rmw => |a| try writer.print("atomic_rmw.{s} %{d}, %{d} {s} : ", .{ @tagName(a.kind), a.ptr.index(), a.operand.index(), @tagName(a.ordering) }),
         .atomic_cmpxchg => |a| try writer.print("atomic_cmpxchg{s} %{d}, %{d}, %{d} {s} {s} : ", .{ if (a.weak) "_weak" else "", a.ptr.index(), a.cmp.index(), a.new.index(), @tagName(a.success_ordering), @tagName(a.failure_ordering) }),
+        .atomic_fence => |a| {
+            try writer.print("atomic_fence {s}\n", .{@tagName(a.ordering)});
+            return;
+        },
         // ── Struct ops ──────────────────────────────────────────
         .struct_init => |agg| {
             try writer.writeAll("struct_init [");