atomics A.3a: swap + fence ops + recognizer, emit bails (lock)

swap (atomicrmw xchg) and a standalone fence wired end-to-end except LLVM
emission (both bail loudly; A.3b makes them real).
- RmwKind += xchg; atomic_swap intrinsic + swap method reuse the atomic_rmw op.
- new atomic_fence op (+ AtomicFence) — ordering-only, void; fence($o)/atomic_fence
  intrinsic; recognizer rejects .relaxed (LLVM has no monotonic fence).
- comptime_vm: xchg = store operand/return old; fence = no-op (single-thread).
- examples 1703 (swap) + 1704 (fence) locked to bails; 1187 (relaxed-fence reject).
- 1186 converted to a direct-intrinsic call → stable user-file diagnostic span
  (the lib-forward-site span shifted when atomic.sx grew — fragile-snapshot fix).

Also fixes a latent A.2 comptime-CAS bug found while here: the success/null
has_value write was 'writeWord(addr, SIZE=0, val=1)' — a 0-byte no-op, correct
ONLY because allocBytes zero-inits (REJECTED-PATTERNS 'coincidentally correct').
Now writes the flag explicitly (size=1, val=0). Suite green (721/0).

src/ir/lower/call.zig

@@ -1723,6 +1723,25 @@ fn atomicOrderingFromNode(self: *Lowering, node: *const Node) ?inst_mod.AtomicOr
 /// scalar of size 1/2/4/8/16. Both constraints are loud diagnostics, never silent
 /// defaults. Returns null if `name` is not an atomic intrinsic.
 pub fn tryLowerAtomicIntrinsic(self: *Lowering, name: []const u8, c: *const ast.Call) ?Ref {
+    // Fence is a standalone op — ordering only, no `$T`/ptr (different shape).
+    if (std.mem.eql(u8, name, "atomic_fence")) {
+        if (c.args.len != 1) {
+            if (self.diagnostics) |d| d.addFmt(.err, c.callee.span, "atomic_fence expects 1 argument", .{});
+            return Ref.none;
+        }
+        const ordering = atomicOrderingFromNode(self, c.args[0]) orelse {
+            if (self.diagnostics) |d| d.addFmt(.err, c.args[0].span, "fence ordering must be a constant ordering literal", .{});
+            return Ref.none;
+        };
+        // LLVM has no monotonic/unordered fence — `.relaxed` is invalid.
+        if (ordering == .relaxed) {
+            if (self.diagnostics) |d| d.addFmt(.err, c.args[0].span, "fence ordering cannot be .relaxed (use .acquire / .release / .acq_rel / .seq_cst)", .{});
+            return Ref.none;
+        }
+        self.builder.emitVoid(.{ .atomic_fence = .{ .ordering = ordering } }, .void);
+        return Ref.none; // fence has a void result
+    }
+
     const is_load = std.mem.eql(u8, name, "atomic_load");
     const is_store = std.mem.eql(u8, name, "atomic_store");
     const rmw_kind = rmwKindFromName(name); // atomic_fetch_add/sub/and/or/xor/min/max
@@ -1875,6 +1894,7 @@ fn rmwKindFromName(name: []const u8) ?inst_mod.RmwKind {
     if (std.mem.eql(u8, name, "atomic_fetch_xor")) return .xor;
     if (std.mem.eql(u8, name, "atomic_fetch_min")) return .min;
     if (std.mem.eql(u8, name, "atomic_fetch_max")) return .max;
+    if (std.mem.eql(u8, name, "atomic_swap")) return .xchg; // swap = exchange RMW
     return null;
 }