64c7db5eb1
Replace the A.0a emit bail with real LLVM atomic codegen: - emitAtomicLoad: LLVMBuildLoad2 + LLVMSetOrdering + LLVMSetAlignment - emitAtomicStore: LLVMBuildStore + LLVMSetOrdering + LLVMSetAlignment (value coerced to the pointee type, mirroring emitStore) - llvmOrdering: explicit sx AtomicOrdering -> LLVMAtomicOrdering map (LLVM's enum is non-contiguous; never an identity cast) examples/1700 now prints 7/42/43; IR is 'load atomic i64, ptr .. seq_cst, align 8' + 'store atomic ..'. Unit test 'emit: atomic load/store (seq_cst, aligned)' locks the emission shape (load atomic/store atomic/seq_cst/align 8) without a fragile full-module .ir snapshot. Suite green (710 examples + units).
78 lines
5.0 KiB
Markdown
78 lines
5.0 KiB
Markdown
# CHECKPOINT-ATOMICS — Stream A (atomics lowering)
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Companion to [PLAN-ATOMICS.md](PLAN-ATOMICS.md). Update after every step (one step at a
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time, per the cadence rule). New corpus category: `17xx`.
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## Last completed step
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**A.0b (green) — DONE.** Real atomic load/store emission: `LLVMBuildLoad2`/`LLVMBuildStore`
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+ `LLVMSetOrdering` + mandatory `LLVMSetAlignment`, ordering via an explicit
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sx-tag→`LLVMAtomicOrdering` switch (`llvmOrdering`). `examples/1700` green (7/42/43); IR
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shows `load atomic i64, ptr … seq_cst, align 8` + `store atomic …`. Added unit test
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`emit: atomic load/store (seq_cst, aligned)` in `emit_llvm.test.zig` (asserts `load
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atomic`/`store atomic`/`seq_cst`/`align 8`). No fragile full-module `.ir` snapshot for 1700
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(it uses `print`); the unit test is the emission-shape gate. Suite green (710 + units).
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### Earlier — A.0a (lock commit)
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Full atomic load/store plumbing with LLVM emission deliberately bailing loudly;
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`examples/1700` locked to the bail diagnostic.
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- `library/modules/std/atomic.sx`: `Ordering` enum, `Atomic($T)` struct (`init`/`load`/
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`store`, **seq_cst-only** — see capability gap below), `atomic_load`/`atomic_store`
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`#builtin` decls. **Opt-in import**, NOT in the universal `std.sx` facade (mirrors
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`trace`) — putting `Ordering` in the prelude grew every program's type table 378→380 and
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churned 37 `.ir` snapshots; reverted.
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- IR ops `atomic_load`/`atomic_store` + `AtomicOrdering` (all 5) + structs (inst.zig);
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print arms (print.zig); comptime_vm arms reuse load/store (single-thread correct);
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recognizer `tryLowerAtomicIntrinsic` (call.zig) — const-ordering-literal guard +
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scalar-size guard, both loud; emit dispatch arms (emit_llvm.zig) → `emitAtomicLoad`/
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`emitAtomicStore` (ops.zig) currently BAIL via `comptime_failed`.
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## Current state
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- A.0a committed; suite green.
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- The recognizer + IR + emit already handle ALL FIVE orderings; only the surface bakes a
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`.seq_cst` literal (the methods can't yet forward a runtime/comptime ordering — gap below).
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- emit bodies are the ONLY placeholder; A.0b swaps them for real builders.
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## Next step
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**A.0b** — replace the `emitAtomicLoad`/`emitAtomicStore` bail with real
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`LLVMBuildLoad2`+`SetOrdering`+`SetAlignment` / `LLVMBuildStore`+`SetOrdering`+
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`SetAlignment` (explicit sx-tag→LLVM ordering switch); regen 1700 → green (7/42/43) + host
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`.ir`; add `emit_llvm.test.zig` unit. Then adversarial review, then the comptime-enum worker
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+ A.0.5 migration to the full ordering surface.
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## Known issues / capability gaps
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- **Comptime-constant ordering propagation MISSING (blocks the full surface).** A runtime
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`Ordering` method param can't reach LLVM (orderings are instruction attributes, not
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operands), and comptime enum value params don't exist (`$o: Ordering` → `o` unresolved in
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body; `resolveValueParamArg` folds integers only). So A.0 ships seq_cst-only; A.0.5 closes
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the gap (worker: implement comptime enum value params) and MIGRATES the methods — NO
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legacy left by stream end.
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- **Latent (observed, not yet filed):** calling an *unrecognized* bodiless `#builtin`
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silently returns 0 / no-ops with exit 0 (that's how 1700 behaved before recognition
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landed) — a silent-fallback footgun in the generic builtin-call path, independent of
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atomics. Flag to user; candidate `issues/` entry.
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## Decisions (Stream A specifics; surface locked in design §4.6)
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- `Atomic($T)` = pure-sx transparent 1-field struct (NO new IR type); ops = `#builtin`
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intrinsics emitted as new IR ops. Minimal compiler surface.
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- Ordering is compile-time-only (const enum literal), baked into the op as a Zig enum;
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non-literal = loud diagnostic. sx tag → LLVM ordering via explicit switch (LLVM enum is
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non-contiguous: 2/4/5/6/7).
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- Atomic load/store REQUIRE explicit alignment (`LLVMSetAlignment`) — verifier mandate.
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- Comptime VM treats atomics as ordinary load/store (single-thread ⇒ correct), not a bail.
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- **Snapshot scope corrected:** `.ir` (LLVM IR) is arch-invariant for atomics → ONE host
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`.ir` per op, not arch-gated x86/aarch64 pairs (they'd be byte-identical). Asm-level arch
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divergence + weak-memory semantics are OUT of corpus scope (stress harness, Stream C).
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## Log
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- **carve** — wrote PLAN-ATOMICS.md + CHECKPOINT-ATOMICS.md; grounded the intrinsic path,
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switch sites, LLVM-C API (no `LLVMBuildAtomicLoad`; use `LLVMBuildLoad2`+`SetOrdering`+
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`SetAlignment`), and corrected the arch-`.ir` misconception (`sx ir` emits arch-invariant
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LLVM IR). Stream ready; A.0a is the first implementation step.
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- **A.0a** — landed lib (atomic.sx, opt-in import) + IR ops (atomic_load/atomic_store +
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AtomicOrdering) + recognizer + print/vm arms + emit BAIL; locked `examples/1700` to the
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bail diagnostic. Reverted a universal-facade wiring that churned 37 `.ir` snapshots
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(Ordering would bloat every program's type table). Suite green (710/0).
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- **A.0b** — real atomic load/store emission (LLVMBuildLoad2/Store + SetOrdering +
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SetAlignment; explicit sx→LLVM ordering switch). 1700 green (7/42/43, `load atomic …
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seq_cst, align 8`). Unit test added. Suite green (710 + units).
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