dd363ca877
First implementation step of Stream B1 (fibers). Make the inert abi(.pure) ABI carry an is_pure flag through lowering, with LLVM emission deliberately bailing loudly until B1.0b — the lock half of the lock->green cadence. - IR Function.is_pure, set from fd.abi == .pure at both declareFunction decl sites. - funcWantsImplicitCtx skips .pure (no synthetic __sx_ctx, mirroring the .c skip): a pure fn reads args from ABI registers, an implicit ctx would occupy a register slot the asm doesn't expect. - both body-lowering paths bypass lowerValueBody for .pure: lower the asm body as statements + cap with unreachable. A pure body has no sx return (the asm rets itself), so the implicit-return diagnostic must not fire. - emit_llvm Pass 2 bails loudly when func.is_pure (build-gating nonzero exit) rather than emit a framed body, whose epilogue would corrupt a context switch's deliberate SP-in != SP-out. examples/1800-concurrency-pure-asm.sx: one host example (no .build pin -- the bail fires before instruction selection, so it is host-independent), locked to the bail snapshot. B1.0b flips emit to LLVM's naked attribute + asm-only body and pins the example per-arch. The sx-facing name is "pure" throughout (field, diagnostic); LLVM's naked attribute is only the B1.0b lowering mechanism. Suite green (722/0).
103 lines
7.1 KiB
Markdown
103 lines
7.1 KiB
Markdown
# CHECKPOINT-FIBERS — Stream B1 (fibers + Io + M:1 scheduler)
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Companion to [PLAN-FIBERS.md](PLAN-FIBERS.md). Update after every step (one step at a time,
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per the cadence rule). New corpus category: `18xx` concurrency.
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## Last completed step
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**B1.0a (`abi(.pure)` lock commit) — DONE.** Plumbed the `is_pure` flag end-to-end and made
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emit bail loudly:
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- IR `Function.is_pure: bool` ([inst.zig](../src/ir/inst.zig)) — set from `fd.abi == .pure`
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at both `declareFunction` decl sites ([decl.zig](../src/ir/lower/decl.zig)).
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- `funcWantsImplicitCtx` returns false for `.pure` (mirrors the `.c` skip, decl.zig:515) —
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a `.pure` fn gets no synthetic `__sx_ctx`.
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- Both body-lowering paths bypass `lowerValueBody` for `.pure`: lower the asm body as
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statements + cap with `unreachable` (a `.pure` body has no sx return — the asm rets
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itself; this avoids the implicit-return diagnostic).
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- `emit_llvm` Pass 2 (~line 402) **bails loudly** when `func.is_pure`
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("`abi(.pure)` function '…' LLVM emission not yet implemented") via `comptime_failed`
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(driver aborts nonzero) — NOT a framed body (whose epilogue would corrupt a context
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switch's SP-in ≠ SP-out).
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- `examples/1800-concurrency-pure-asm.sx` — one host example (no `.build` pin; the bail is
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host-independent, fires before any asm/instruction selection), locked to the bail snapshot
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(exit 1, empty stdout, the loud diagnostic on stderr).
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- **Naming:** the sx-facing name is **`pure`** throughout (field, diagnostic); LLVM's
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`naked` attribute is only the B1.0b lowering mechanism (per user direction — don't call
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the function "naked").
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- `zig build && zig build test` green: **722 ran, 0 failed**.
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## Current state
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Stream A (atomics) is feature-complete (✅) and unblocks B2-channels. Stream B1: **B1.0a
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landed**; the `abi(.pure)` ABI is plumbed but emit deliberately bails (B1.0b flips it to
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real LLVM `naked` emission). No fibers/Io/scheduler code yet. Grounded floor facts:
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- `context` is already an implicit `*Context` param (slot 0) + `push Context` is a stack
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`alloca` ⇒ **fiber-local for free**. Only shared root = `__sx_default_context` global
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(entry-point bind). B1.1 expected to be a **library convention** (spawn trampoline
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snapshots the spawner's ctx into slot 0), **likely zero compiler change** — probe first.
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- Inline asm works end-to-end (lower→emit→JIT, aarch64 + x86_64) — the `.pure` body reuses it.
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## Next step
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**B1.0b (`abi(.pure)` real emission)** — per PLAN-FIBERS.md "Phases → B1.0 → B1.0b" and the
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kickoff prompt at the bottom of that file. Replace the emit bail with LLVM's `naked`
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attribute + asm-only body; pin `1800` aarch64 (run end-to-end → exit 42, capture `.ir`); add
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x86_64 cross sibling `1801` (ir-only); add an `emit_llvm.test.zig` unit test asserting the
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`naked` attr. Separate commit (cadence rule — B1.0a locked, B1.0b greens).
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## Known issues / capability gaps
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- **Orthogonal (not a B1 blocker):** default VALUES for comptime params don't bind on
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generic-struct methods (free-fn defaults DO work) — inherited from Stream A. Only matters
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if a B2 lib type wants a defaulted comptime param; atomics/fibers require explicit, so
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unaffected.
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- **Issue 0144 (open, independent):** calling an unrecognized bodiless `#builtin` silently
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returns 0 / exit 0 — a silent-fallback footgun in the generic builtin-call path. Filed;
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leave for its own fix session unless prioritized. Not a B1 blocker.
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- **Deferred design gap (documented):** the B1.4 event-loop `Io` does not yet cooperate with
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a platform UI run loop (CFRunLoop/NSRunLoop/ALooper); pinning gives thread-affinity, not
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run-loop integration — a §6 app-target concern, out of B1 scope.
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## Decisions (Stream B1 specifics; surface locked in design §4 / §4.6)
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- **The async runtime is sx LIBRARY code.** The compiler provides only: the general
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primitives (inline asm ✅, `abi(.pure)` naked [B1.0], atomics ✅) + fiber-safe codegen
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(`context` already fiber-local — B1.1). Schedulers, fibers, channels, futures, `Io`
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vtables, `mmap` stacks are all sx.
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- **`abi(.pure)` is the real spelling of the design's `callconv(.naked)`** — postfix slot,
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`name :: (sig) -> Ret abi(.pure) { asm { … }; }`. B1.0 = carry it into IR + emit LLVM
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`naked` + skip prologue/ctx (mirror the existing `.c` skip), NOT extend the enum (it's
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already there, just inert).
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- **`.pure` ≠ `.c`:** a `.c` epilogue would restore SP from the wrong stack across a context
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switch (SP-in ≠ SP-out by design). `.pure` = no prologue/epilogue/frame; the asm emits its
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own `ret`. This is why the switch must be `.pure`.
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- **Naming:** sx-facing name is **`pure`** (field `is_pure`, the diagnostic). LLVM's `naked`
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function attribute is only the lowering mechanism (B1.0b) — do not call the function
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"naked" (user direction).
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- **B1.0 snapshot scope:** a `.pure` body is raw per-arch asm; LLVM's `naked` attr text is
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arch-invariant. **B1.0a** = one host example locked to the emit bail (host-independent —
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fires before instruction selection; no `.build` pin). **B1.0b** = pin aarch64 + add an
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x86_64 cross sibling (`.build` target-gated, ir-only on mismatch), like the asm corpus
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split. The `.ir` proves the `naked` attr + asm emitted, NOT register-save correctness
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(that's B1.3's stress harness).
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- **B1.1 grounded as library-only (pending probe):** push frames are stack-`alloca`'d and
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the implicit ctx rides slot 0, so a spawn trampoline can pass a snapshotted ctx with no
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compiler change. The design doc's "never raw TLS" guards a non-problem (context is not
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TLS). Probe to confirm before sizing any compiler work.
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- **Test keystones (design §10):** the **B1.3 switch-stress harness** gates the
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context-switch (the one piece the deterministic `Io` can't test — §8.1.1, §10.7); the
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**B1.4 deterministic-sim `Io`** (calibrated against blocking `Io` — §8.1.3) gates all
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scheduling tests. Both must exist + be calibrated before the async tests they gate are
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trusted. `18xx` asserts program-emitted ordering contracts, not raw interleaving.
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## Log
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- **carve** — wrote PLAN-FIBERS.md + CHECKPOINT-FIBERS.md. Grounded the B1 compiler floor:
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`ABI.pure` inert (type_resolver.zig:237), IR `Function` has no naked flag (inst.zig:605),
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attribute API pattern (emit_llvm.zig:1339 nounwind), `.c` ctx-skip precedent
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(decl.zig:515), `push Context` stack-alloca + slot-0 implicit ctx (stmt.zig:1263,
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lower.zig:259), `__sx_default_context` root (decl.zig:2667/2815), inline-asm corpus
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(1645/1651). Corrected the design's `callconv(.naked)` → real `abi(.pure)` spelling and
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the B1.0 snapshot story. B1.1 grounded as likely library-only. Baseline green (721/0).
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- **B1.0a** — plumbed `Function.is_pure` (set from `fd.abi == .pure` at both decl sites);
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`funcWantsImplicitCtx` skips `.pure` (no implicit ctx, like `.c`); both body-lowering
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paths bypass `lowerValueBody` for `.pure` (asm body + `unreachable` cap — no sx return);
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`emit_llvm` Pass 2 bails loudly on `func.is_pure`. `examples/1800-concurrency-pure-asm.sx`
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locked to the bail (exit 1 + diagnostic). Renamed `is_naked`→`is_pure` per user direction
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(sx says `pure`, not "naked"; LLVM `naked` attr is only the B1.0b mechanism). Suite green
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(722/0). **Next: B1.0b (real `naked` emission).**
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