ea1faf7b69
issue 0151 (generic $T inference through generic-struct / pointer / UFCS-pack params) is fixed and committed, so io.sx's async/await/cancel are now callable in every form. Building the async examples then tripped a SEPARATE codegen bug: Atomic(bool) emits a sub-byte (i1) atomic load/store that fails LLVM verification (must be byte-sized). Future.canceled: Atomic(bool) hits it. Filed issues/0152 with a standalone repro + investigation prompt (codegen fix in src/backend/llvm/ops.zig — promote sub-byte atomics to i8 storage). Per the STOP rule, paused B1.2's async examples (1805/1806) pending the 0152 fix. Checkpoint updated: 0151 RESOLVED, async surface BLOCKED on 0152.
80 lines
3.2 KiB
Markdown
80 lines
3.2 KiB
Markdown
# 0152 — `Atomic(bool)` emits a sub-byte (i1) atomic load/store that LLVM rejects
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## Symptom
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`Atomic(bool)` lowers `bool` to LLVM `i1` and emits the atomic load/store
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at that type. LLVM requires atomic memory accesses to be byte-sized, so
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codegen fails verification:
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```
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LLVM verification failed: atomic memory access' size must be byte-sized
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i1 store atomic i1 %load5, ptr %gep release, align 1
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i1 %atomic_load = load atomic i1, ptr %gep11 acquire, align 1
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```
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- `Atomic(i64)`, `Atomic(i32)`, … → fine (byte-sized).
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- `Atomic(bool)` → LLVM verifier error (i1 is 1 *bit*, not byte-sized).
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## Reproduction
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Standalone — depends on no project symbols beyond `modules/std.sx` +
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`modules/std/atomic.sx`:
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```sx
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#import "modules/std.sx";
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#import "modules/std/atomic.sx";
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main :: () -> i32 {
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a := Atomic(bool).init(false);
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a.store(true, .release);
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if a.load(.acquire) { print("yes\n"); } else { print("no\n"); }
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return 0;
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}
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```
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Expected: prints `yes`. Actual: LLVM verification failure (i1 atomic).
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## Impact
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Blocks the B1.2 async surface. `library/modules/std/io.sx`'s
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`Future($R)` carries a `canceled: Atomic(bool)` cancellation flag (atomic
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so a future scheduler thread can flip it). `async`/`cancel`/`await` all
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touch it (`Atomic(bool).init`, `.store(true, .release)`,
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`.load(.acquire)`), so the async examples (`1805`/`1806`) cannot build.
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This is independent of issue 0151 (generic inference) — that is now fixed,
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which is what newly exposed this codegen path.
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## Investigation prompt
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The atomic load/store emitters in `src/backend/llvm/ops.zig`
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(`emitAtomicLoad` ~line 387, `emitAtomicStore`, `emitAtomicRmw`,
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`emitAtomicCmpxchg`) use `toLLVMType(instruction.ty)` directly as the
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atomic access type. For a `bool` element that is `i1`, which LLVM rejects
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for atomics (must be a byte-multiple).
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The fix should promote a sub-byte atomic to its byte-sized storage type:
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load/store as `i8` (the ABI storage type for `bool`) and `trunc`/`zext`
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between `i1` and `i8` at the value boundary — mirroring how a non-atomic
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`bool` field is already stored as a byte. Apply consistently across
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load / store / rmw / cmpxchg so an `Atomic(bool)` round-trips. Confirm the
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alignment (`LLVMSetAlignment`) uses the promoted byte size.
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Possible alternative: have `Atomic($T)` (in `library/modules/std/atomic.sx`)
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constrain / widen a `bool` element to a byte-sized integer in the type
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itself — but the codegen-level promotion is more robust (any i1-typed
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atomic, however it arises, becomes legal).
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Verification: run the repro above; expect `yes`. Then restore
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`examples/1805-concurrency-io-blocking-async.sx` (+ add `1806` cancel) per
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Stream B1 / CHECKPOINT-FIBERS and confirm the async surface builds and runs
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(`sum: 42` / `double: 42`, cancel → `.canceled`).
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### Possibly-related secondary symptom (verify after the i1 fix)
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The same async probe also tripped an `or`-merge PHI type mismatch
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(`%bp = phi i1 [ true, … ], [ 0, … ]`) when `f.await() or { <i64> }` was
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lowered. A minimal `(i64, !E)` + `or { -1 }` does NOT reproduce it, so this
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may be entangled with the malformed `Atomic(bool)` field in the `Future`
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struct rather than a second bug. Re-check once the i1 atomic is fixed; if it
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persists, file separately.
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